Supplier of bus interfaces, flight recorders, simulation and analyzer solutions for the avionics industry.



Honeywell Flight Controls P2P

Built for Honeywell Flight Control Electronics simulation and test, the P2P resource provides capabilities for monitoring, simulation, error injection and test of FCE P2P busses, also referred to as InterModule Bus (IMB) and Actuation Data Bus (ADB). The P2P resource consists of a processor and IO module on a suitable carrier. The intelligence provided by the processor allows the P2P resource to autonomously monitor or simulate FCE bus traffic. We have IO modules of 32 direct or 20 transformer coupled channels each configurable as to LRU/channel type.  By having embedded knowledge of LRU type, the P2P resource performs the same protocol generation and checking as the actual LRUs.  When in simulation mode a channel transmits with the same timing and protocols of the actual LRU.  LRU emulation of FCM, ACE, REU, and DMRS traffic is supported. 

Error injection capabilities of the P2P resource include the generation of packet length errors, CRC errors, loss of post amble and bus frequency modification.  In addition bus passthru allows inserting the card between LRUs for modification of data from one LRU to another. 

Our companion analyzer product, the Goebelyzer makes use of the P2P resource capabilities. Packet data is displayed in engineering units based on ICD data definitions. The analyzer can be extended with Gtools suite of productivity tools to provide control, scripting, bus mastering and replay of FCE bus traffic.

P2P processor module

  1. > Simulation of REU receive/transmit of ACE channels

  2. > Simulation of ACE transmit/receive of REU channels

  3. > Simulation of DMRS transmit to ACE channels

  4. > Simulation of FCM transmit/receive of ACE including encrypted wrap

  5. > Simulation of ACE receive/transmit of FCM including encrypted wrap

  6. > Simulation of FCM to FCM inter cabinet channels

  7. > Firmware upgradeable to include custom test capabilities

  8. > Scheduling of transmit data to 1 microsecond accuracy

  9. > Timing of receive data to 1 microsecond accuracy

  10. > PowerPC 440GX processor @ 667 MHz 128MB SDRAM 256KB SRAM

P2P IO module

  1. > FPGA design allows configuration of each channel

  2. > 5M and 400K bit per second channels

  3. > Channel speeds variable +/- 20%

  4. > Hardware error injection control, length, CRC, post amble